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Technical and applications information written and presented
by Sigrity at conferences and in publications devoted to electronic design strategies.
Sigrity customer technical papers can be found at
Customer
Success Stories.
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Papers |
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42. |
Concurrent Planning and
Feasibility for Efficient Package-on-Package (PoP) Design
[ECTC], May 26, 2009.
Package-on-Package (PoP) implementations have
grown at a 40% compound annual growth rate. Compact
form factor, configurability, test and sourcing flexibility
are often mentioned as benefits. The key to efficient PoP
devices is early design planning. A flow that supports
assessment of package to package interface options is a
central element to the flow as is early IO pad ring
layout planning. The paper describes solutions for handling
the complex IO implications
for PoP and other multi-die designs.
Related Sigrity products:
OrbitIO Planner.
Paper (PDF Format)  Presentation (PDF Format)
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41. |
A Low-Cost Task Specific Solution for IO
Pad-Ring and Package Net List Construction
May 2009
Identifying downstream connectivity issues early enables
improvement while options are cost effective. This paper
describes typical flow and tool barriers to chip-to-package
net list coordination. Sigrity's IC Net Planner is introduced.
With a familiar spreadsheet paradigm and graphic visualization Net
Planner facilitates rapid exploration of the solution
space to reduce iterations and save time.
Related Sigrity products:
OrbitIO Planner.
Paper (PDF Format)  Webinar Information
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40. |
Codesign Enables Rapid Development and High Performance
[Solid State Technology], April 2009.
There are significant benefits associated with parallel chip/package/board
codesign flows. Time to market savings are achieved through collaborative feedback
and managing physical and electrical constraints across the design. The approach
serves to greatly reduce the risk of design failure while at the same time
enabling lower cost downstream implementation options.
Related Sigrity products:
XtractIM,
PowerSI,
XcitePI and
OrbitIO Planner.
Article (Web Link ...)
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39. |
DC Design Squeeze
[Printed Circuit Board Design and Fabrication], February 2009.
The voltage margins available for designers for DC have become extremely
compressed. Multiple voltage domains and the impact of plane geometry irregularities
exacerbate the issues. The article also discusses the ability to automatically pinpoint
the best remote sense location to significantly impact DC margin. Design teams that
effectively handle DC through the board and package design process are rewarded with
additional confidence and margin to handle AC noise.
A case study is described where a plane layer is removed safely in a design.
Related Sigrity products:
PowerDC.
Article (Web Link ...) (PDF Format)
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38. |
System IO Planning and Design
Feasibility - Challenges and Solutions
[DesignCon], February 4, 2009.
Industry trends and challenges associated with system IO planning are discussed
in this paper. A new methodology is introduced that takes advantage of specially targeted
software that is designed to handle chip, package and printed circuit board information.
This new approach enables
dynamic system IO planning across domains.
Related Sigrity products:
OrbitIO Planner.
Paper (PDF Format) Presentation (PDF Format)
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37. |
High-Speed Channel Designs - IBIS AMI Model Solution
[DesignCon], February 3, 2009.
This presentation was given as part of a panel focused on channel design.
It highlights the Algorithmic Modeling Interface (AMI) modeling standard which
became available in August of 2008 with IBIS version 5. The standard allows chip
developers to create executable black box models of transmitter and receiver behavior.
With these models, systems developers can perform early architectural studies with
confidence that the models they are using will be interoperable between suppliers.
AMI transmitter and receiver models play a vital role in
simulations of channel behavior as designs progress.
Related Sigrity products:
Channel Designer.
Presentation (PDF Format)
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36. |
PCB Signal Integrity, Power Integrity and EMC Challenges
[PCD&F], December 1, 2008.
SI, PI and EMC challenges are interrelated. This paper
discusses the implications of coupling among traces as well as
planes, vias and other design structures. Current loops and two
terminal voltages make SI and PI issues virtually indistinguishable.
Careful handling of SI and PI are also important to prevent EMC
problems. This gives rise to the imperative for system-level
analysis to analyze these combined challenges. Sigrity's hybrid solver
approach provides needed accuracy with practical run times.
Related Sigrity products:
PowerSI and
SPEED2000.
Article (Web Link ...) (PDF Format)
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35. |
Addressing 3D Packaging Challenges
November 24, 2008.
This paper focuses on issues that exist for those designing packages with
stacked-die, package-on-package (PoP) and thru-silicon-via (TSV) implementations.
These designs are growing in importance and require analysis approaches that
account for 3D effects and physical implementation that assure complex structures
such as cantilevered wirebond are designed for manufacturability.
Early design planning is also key for these multi-die design where IO pad
ring and package-to-package connectivity is of growing importance.
Related Sigrity products:
UPD,
OrbitIO Planner and
XtractIM
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Paper (PDF Format)
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34. |
A Resonance-Free Power Delivery System Design
Methodology Applying 3D Optimized Extended Adaptive Voltage Positioning.
[EPEP Poster Session], October 27, 2008.
The paper describes the use of EAVP (Extended Adaptive Voltage Positioning)
to select capacitors for the power delivery system of a system that included a six
layer package with an eight layer board. An optimization is performed that considers
both performance and cost that effectively results in a resonance-free design.
Related Sigrity products:
OptimizePI.
Presentation (PDF Format)
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33. |
Will it Work?
[SOCcentral], September 2, 2008.
Without explicit design consideration of off-chip effects, it is
difficult to assure a chip design will operate properly in a customers system.
Design adjustments among the chip, package and even board physical domains
can yield power integrity performance enhancement as well as cost savings,
while avoiding the risk of chip failure when implemented in a system.
Related Sigrity products:
XcitePI,
SPEED2000 and
XtractIM
Article (Web Link ...) (PDF Format)
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32. |
Electrical Modeling and Model Representations for Package
Interconnects and Power Delivery Networks
[IBIS Forum at DAC], June 10, 2008.
Presentation describing the range of modeling approaches and the impact on accuracy
with recommendations for extensions to the IBIS standard. Related Sigrity products:
XtractIM and
PowerSI
Presentation (PDF Format)
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31. |
A New Power Delivery System Design Practice
[PCB007], January 30, 2008.
Article comparing traditional PCB power delivery system design approaches
to new methods which provide cost savings along with analytically assured
performance. Related Sigrity products:
OptimizePI
Presentation (PDF Format)
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30. |
Efficient Signal and Power
Integrity Analysis Using Parallel Techniques
[EPEP] Electrical Performance of Electronic Packaging, 2007.
Presentation describing parallel computing technology to
use multi-processors in a singly system or across a network to
increase simulation throughput. Related Sigrity products:
PowerSI,
OptimizePI and
XtractIM
Paper (PDF Format)
Presentation (PDF Format)
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29. |
Mastering the I/O Planning Puzzle
[EETimes] September 24, 2007.
The key to system-wide IO planning is to achieve balance across all
domains of the system so key decision criteria can be evaluated in
the full system context to guide design decisions.
Related Sigrity products:
OrbitIO Planner
Paper (PDF Format)
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28. |
Integrity Drives Successful Electronic Product Design
[EETimes] August 27, 2007.
In this article Sigrity and Magma technical staff members describes important
considerations for chip-package-board power and signal integrity analysis.
Related products:
PowerSI,
XtractIM and
OptimizePI.
Paper (PDF Format)
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27. |
Cost-Optimized PCB Power Integrity Design
[PCD&M] Printed Circuit Design & Manufacture Magazine, March 2007.
New analysis tools measure the performance of the power
delivery system and consider both cost and electrical
performance resulting in a functional and cost-efficient
design. Related Sigrity products:
OptimizePI.
Paper (HTML Format)
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26. |
A Review of PCB-level Power Delivery System
EE Times, Asia, China and Korea, May/June 2006
Improve power delivery system performance by understanding
the fundamental issues in design, and doing extensive
modeling and simulation of the entire PDS. Related Sigrity products:
PowerSI and
PowerDC.
Paper (PDF Format, English)
Paper (PDF Format, Chinese)
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25. |
Fundamentals of S-Parameter Modeling for Power Distribution System (PDS) and SSO Analysis
[IBIS Summit] Anaheim, CA, June 2005.
Related Sigrity products:
PowerSI and
PowerDC.
Presentation (PDF Format)
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24. |
IR Drop in High-Speed IC Packages and PCBs
[PCD&M] Printed Circuit Design & Manufacture Magazine, April 2005.
Neckdowns, low-weight copper and Swiss cheese effects are
conspiring to wreak havoc on your high-speed design. Get the
drop on them. Related Sigrity products:
PowerDC.
Paper (PDF Format)
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23. |
On-Chip Power Integrity, Including Package Effects
[SoC] SoCcentral Online Articles, March 14, 2005
On-chip power integrity effects and their influence on the entire power delivery system
have become a major concern in the design of large and complex high-speed SoC designs. Today's extreme design challenges
require a complete power-aware solution that encompasses the global
effects of the entire power delivery system, including the realistic effects of the package
and the PC board on the functional operation of the IC.
Written by Dr. Fang and John Kane.
Related Sigrity products:
CoDesign Studio,
XcitePI,
SPEED2000.
Paper (PDF Format)
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22. |
An Initial Case Study for BIRD95: Enhancing IBIS for SSO Power Integration Simulation
DesignCon, 2005.
This presentation is an overview on how BIRD95 can potentially help improve IBIS models.
Related Sigrity products:
SPEED2000.
Presentation (PDF Format)
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21. |
A Fast Evaluation of Power Delivery System Input Impedance of Printed Circuit Boards with Decoupling Capacitors
[EPEP] Electrical Performance of Electronic Packaging, 2004.
A fast power delivery system input impedance evaluation methodology for printed circuit board decoupling capacitor placement study is presented in this paper.
Related Sigrity products:
PowerSI and
Broadband SPICE.
Paper (PDF Format)
Presentation (PPT Format)
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20. |
Recent Developments in Polyimide-Based Planar Capacitor Laminates
[ICEP] International Conference on Embedded Passives, June 2004.
This paper discusses performance and reliability data of both unfilled and ceramic-filled
polyimide-based thin core laminates for use as embedded planar capacitor layers.
A short overview of a simulation tool’s prediction of the impact of increasing
the dielectric constant between power and ground will also be discussed.
Related Sigrity products:
PowerSI and
SPEED2000.
Paper (PDF Format)
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19. |
Using Signal Integrity Analysis to Achieve EMC
[PCD&M] Printed Circuit Design & Manufacturing Magazine, April 2004.
This paper discusses how some EMC engineers use signal integrity to help improve EMI performance
and shorten testing times.
Related Sigrity products:
SPEED2000 and
PowerSI.
Article (PDF Format)
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18. |
The Power of Planes - Low Impedance Power Delivery Over Broad Frequencies
[PCD&M] Dr. Jiayuan Fang and Dr. Jin Zhao, Printed Circuit Design &
Manufacturing Magazine, Sept. 2003.
Related Sigrity products:
PowerSI and
SPEED2000.
This paper discusses low-impedance power delivery over broad frequencies, specifically
how decoupling capacitors reduce impedances at low frequencies while removing resonances up to
a few hundred MHz.
Paper (PDF Format)
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17. |
Measured and Simulated Signal Propagation Behavior on High Speed Nets of Large, High Dense, and Complex PCBs
[spi2003_Miersch]
The purpose of this paper is to evaluate, quantitatively, the influence of the individual
parasitic parameter groups like on-board nets, chip packages, on-chip parameters on the total
net performance of the simulation.
Related Sigrity products:
SPEED2000 and
PowerSI.
Paper (PDF Format)
Presentation (PDF Format)
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16. |
Effective Decoupling Radius of Decoupling Capacitor
[epep2001_Chen]
Decoupling capacitors on packages and printed circuits
boards are often essential to reduce
voltage fluctuations and maintain
power and signal integrity. This paper presents a method
for the evaluation of effectiveness of
decoupling capacitors placed on package or board structures.
Related Sigrity products:
PowerSI.
Paper (PDF Format)
Presentation (HTML Format)
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15. |
Signal Integrity
[EMC-IEEE]
Book Chapter, Engineering Electromagnetic Compatibility, Second Edition,
IEEE Press and John Wiley & Sons, Inc., 2001
In this chapter, we will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues.
Several software tools available at present for signal integrity analysis and current trends in this area will
also be introduced.
Related Sigrity products:
SPEED2000.
Paper (PDF Format)
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14. |
Effects of 20-H Rule and
Shielding Vias on Electromagnetic Radiation From Printed
Circuit Boards
[epep_2000]
This
paper investigates the effects of the 20-H rule and
shielding vias on the radiation from printed circuit boards.
For the two-plane structure, 20-H rule yields much more
radiation than the normal structure. For the multiple plane
case, no significant change in radiation is found if the
20-H rule is applied to the internal planes. Also, the
numerical result shows that the usage of shielding vias
would cut down the radiation effectively.
Related Sigrity products:
SPEED2000.
Paper
(PDF Format)
Presentation (HTML Format)
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13. |
Modeling
of the Electrical Performance of the Power and Ground Supply
for a PC Microprocessor on a Card
[epep98_amd]
October 26, 1998
The electrical characteristics of power and ground supply of a PC microprocessor packaged
in a BGA mounted on a PCB are studied with electromagnetic field analysis.
The effects of decoupling capacitor types and locations is investigated to achieve the
goals of low power and ground impedance and no or insignificant resonances inside the package.
Related Sigrity products: SPEED97
Paper
(PDF Format)
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12. |
Effects
of Power/Ground Via Distribution on the Power/Ground
Performance of C4/BGA Packages
[epep98_zhao]
October 26, 1998
This paper studies the effects of the distribution of power and ground vias in BGA packages.
Strategies that rely on vias concentrated in the core area is compared to uniform distribution.
The performance is then evaluated in terms of resonance, impedance and effective inductance.
Related Sigrity products: SPEED97
Paper
(PDF Format)
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11. |
Extraction
of Equivalent Circuit Models of Package Power Supply
Distribution Systems from Full Wave EM Field Simulations
[epep98_moll]
October 26, 1998
The extraction of circuit models for package power supply distribution systems from the
results of full wave EM simulations is addressed. Both time and frequency domain optimizations
are used for the extraction. Related Sigrity products: SPEED97
Paper
(PDF Format)
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10. |
Validity
of Mutual Inductor Model for Electromagnetic Coupling
between Vias in Integrated-Circuit Packages and Printed
Circuit Boards
[ectc98]
May 25, 1998
A validity study of mutual inductor model for electromagnetic coupling between
vias is presented in this paper. Comparisons are made between the mutual inductor
model and full-wave field simulation. Limitations associated with the lowest resonant
frequency are identified with electromagnetic simulation.
Related Sigrity products: SPEED07
Paper
(PDF Format)
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9. |
Where to
Place Decoupling Capacitors ? -- Answer to a Problem Posted
on SI-List
[reply]
February 13, 1998
A discussion of the potential benefit associated with placing a capacitor at the
site of a via even there are no adjacent components. Various electromagnetic
simulations are performed to assess the variations of no decap, decap near via,
decap near switching current source. Related Sigrity products: SPEED97
Discussion
(HTML Format)
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8. |
Shorting
Via Arrays for the Elimination of Package Resonance to
Reduce Power Supply Noise in Multi-layered Area-Array IC
Packages
[ipdi98]
February 2, 1998
This paper presents full-wave electromagnetic field simulations on the effects of
shorting via arrays for the reduction of power and ground noise. Properties of
internal resonance in multi-layer packages are studied.
Related Sigrity products: SPEED97
Paper
(HTML Format) |
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7. |
Significance
of Electromagnetic Coupling Through Vias in Electronics
Packaging
[epep97]
October 27, 1997
The investigation on the relative significance of electromagnetic coupling between vias
and parallel traces is presented in this paper. The study shows the coupling between
vias can often be stronger than the coupling between traces. Related Sigrity products: SPEED97
Paper
(HTML Format) |
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6. |
The
Facts about the Input Impedance of Power and Ground Planes
[inputimp]
July 31, 1997
Power and ground planes may connect to the power supply at several locations.
Moreover, a number of decoupling capacitors may be connected to the power and
ground planes. Behavior at the low frequency limit is explored.
Related Sigrity products: SPEED97
Paper
(HTML Format) |
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5. |
Reduction of Power and Ground Noise Coupling in Mixed Signal Modules
[epep96]
October, 1996
This paper covers the effectiveness of full-wave electromagnetic field simulation to
identify and reduce power and ground noise coupling in mixed signal modules.
Strategies associated with segmentation of the power and ground planes and proper
placement of decoupling capacitors for the reduction of noise coupling are evaluated.
Related Sigrity products: SPEED97
Paper
(PDF Format)
Presentation (HTML Format) |
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4. |
Optimum
Placement of Decoupling Capacitors on Packages and Printed
Circuit Boards Under the Guidance of Electromagnetic Field
Simulation
[ectc96o]
May 28, 1996
This paper presents an efficient signal integrity analysis technique for identifying
voltage fluctuations on power/ground planes in complex packaging structures.
Statistical noise voltage distributions can be used to assess the effectiveness of
decoupling capacitor placement. The implications of value, number and location of
decoupling capacitors is explored. Related Sigrity products: SPEED97
Paper
(PDF Format) |
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3. |
Measurement
and Simulation of Simultaneous Switching Noise in the
Multi-Reference Plane Package
[ectc96m]
May 28, 1996
The paper covers a laboratory experiment representing simultaneously switching circuits in
a multi-reference plane design. Experimental data is compared to theoretical calculations
and to simulated data from three modeling techniques of progressive complexity including
lumped element, hybrid lumped element / transmission line and full wave solutions.
Related Sigrity products: SPEED97
Paper
(PDF Format) |
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2. |
Extraction
of Transient Behavioral Model of Digital I/O Buffers from
IBIS
[ectc96ibis]
May 28, 1996
Extraction and simulation of transient behavioral models of state transition of digital
I/O buffers is introduced. A new approach is described which enables interconnect
simulations with large numbers of simultaneously switching devices while maintaining
accuracy compared to corresponding transistor level models.
Related Sigrity products: SPEED97
Paper
(PDF Format) |
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1. |
A New
Approach to Signal Integrity Analysis of High-Speed
Packaging
[epep95]
October 2, 1995
This paper describes an approach that simultaneously performs electromagnetic field
simulation and circuit simulation. The electromagnetic field simulation algorithms
leverage understanding of the unique geometric features of package and board structures
to run two to four orders of magnitude faster than general-purpose electromagnetic simulators.
The accuracy of simulated results are verified by lab measurements.
Related Sigrity products: SPEED97
Paper
(PDF Format) |
